1. Field of the Invention
The present invention relates to a method of fabricating a trench capacitor, especially to a method of fabricating a trench capacitor having high capacitance for the semiconductor manufacturing technology below the sub-micrometer scale.
2. Related Art
The dynamic random access memory (DRAM) has been widely used in the computer and electronic products for storing digital information on arrays of memory cells in the form of charge stored on a capacitor. Each memory cell consists of a single access transistor and a single storage capacitor. Refer to FIG. 1 for showing the circuit diagram of a conventional DRAM memory cell. A DRAM memory cell 1 consists of an NMOS transistor 11 and a capacitor 12. The NMOS transistor 11 includes a gate electrode 111 electrically connected to a word line 13 (WL) and a drain electrode 112 electrically connected to a bit line 14 (BL). One terminal of the capacitor 12 is electrically connected to an operation voltage 121 (1/2 VCC). The other terminal of the capacitor 12 is electrically connected to the source electrode 113 of the transistor 11. The NMOS transistor 11 operates as a switch in response to the signal on the word line 13. When the signal on the word line 13 is 1 (High), the NMOS transistor 11 is turned on, which causes the digital data on the bit line 14 to be stored in the capacitor 12. On the other hand, when the signal on the word line 13 is 0 (Low), the NMOS transistor 11 is cut-off, which causes the capacitor 12 to latch a signal.
The storage capacitors are formed by etching trenches in the substrate in each of the cell areas, commonly referred to as trench capacitors. They may also be formed over the access transistors in the cell areas by depositing and patterning conducting layers over the access transistors, commonly referred to as stacked capacitors.
Refer to FIG.2 for showing the structure of a conventional trench capacitor 2. It includes a semiconductor substrate 21, a diffusion layer 22, a dielectric layer 23, and an upper electrode 24. The diffusion layer 22 acts as the bottom electrode of the trench capacitor 2. The dielectric layer 23 is usually formed by an oxide/nitride/oxide (ONO) layer for acting as the dielectric layer of the trench capacitor 2. The upper electrode 24 is formed by a polysilicon layer.
From the illustration of FIG. 2, it would be obvious that the capacitance of the trench capacitor 2 increases as the contact area between the diffusion layer 22 and the dielectric layer 23 increases. However, since each capacitor lie within an area cannot be larger than the size of the cell area in order to accommodate all the capacitors in the large array of cells used on the DRAM device. It is becoming increasingly difficult to fabricate more memory cells on a DRAM device while limiting the overall DRAM device area to a practical size without decreasing the cell area. In that case, as the cell area decreases, the available area for the storage capacitor in each cell also decreases. This makes it difficult to maintain sufficient capacitance.